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<title>Floating-gate MOSFET</title>

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<span id="openzim-page-title" class="mw-page-title-main"><span class="mw-page-title-main">Floating-gate MOSFET</span></span>

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<p>The <b>floating-gate MOSFET</b> (<b>FGMOS</b>), also known as a <b>floating-gate MOS transistor</b> or <b>floating-gate transistor</b>, is a type of <a href="Metal%E2%80%93oxide%E2%80%93semiconductor_field-effect_transistor" class="mw-redirect" title="Metal–oxide–semiconductor field-effect transistor">metal–oxide–semiconductor field-effect transistor</a> (MOSFET) where the gate is electrically isolated, creating a floating node in <a href="Direct_current" title="Direct current">direct current</a>, and a number of secondary gates or inputs are deposited above the floating gate (FG) and are electrically isolated from it. These inputs are only <a href="Capacitive_coupling" title="Capacitive coupling">capacitively</a> connected to the FG. Since the FG is surrounded by highly resistive material, the charge contained in it remains unchanged for long periods<sup id="cite_ref-Tunneling_1-0" class="reference"><a href="#cite_note-Tunneling-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> of time, typically longer than 10 years in modern devices. Usually <a href="Field_electron_emission#Fowler–Nordheim_tunneling" title="Field electron emission">Fowler-Nordheim tunneling</a> and <a href="Hot-carrier_injection" title="Hot-carrier injection">hot-carrier injection</a> mechanisms are used to modify the amount of charge stored in the FG.

</p><p>The FGMOS is commonly used as a floating-gate <a href="Memory_cell_(computing)" title="Memory cell (computing)">memory cell</a>, the <a href="Computer_memory" title="Computer memory">digital storage</a> element in <a href="EPROM" title="EPROM">EPROM</a>, <a href="EEPROM" title="EEPROM">EEPROM</a> and <a href="Flash_memory" title="Flash memory">flash memory</a> technologies. Other uses of the FGMOS include a neuronal computational element in <a href="Neural_network" title="Neural network">neural networks</a>,<sup id="cite_ref-Mead_2-0" class="reference"><a href="#cite_note-Mead-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Holler_3-0" class="reference"><a href="#cite_note-Holler-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> analog storage element,<sup id="cite_ref-Mead_2-1" class="reference"><a href="#cite_note-Mead-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> <a href="Digital_potentiometer" title="Digital potentiometer">digital potentiometers</a> and single-transistor <a href="Digital-to-analog_converter" title="Digital-to-analog converter">DACs</a>.

</p>

<div class="mw-heading mw-heading2"><h2 id="History">History</h2></div>

<p>The first <a href="MOSFET" title="MOSFET">MOSFET</a> was invented by <a href="Mohamed_Atalla" class="mw-redirect" title="Mohamed Atalla">Mohamed Atalla</a> and <a href="Dawon_Kahng" title="Dawon Kahng">Dawon Kahng</a> at <a href="Bell_Labs" title="Bell Labs">Bell Labs</a> in 1959, and presented in 1960.<sup id="cite_ref-computerhistory_4-0" class="reference"><a href="#cite_note-computerhistory-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> The first report of a FGMOS was later made by Dawon Kahng and <a href="Simon_Min_Sze" class="mw-redirect" title="Simon Min Sze">Simon Min Sze</a> at Bell Labs, and dates from 1967.<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> The earliest practical application of FGMOS was floating-gate <a href="Memory_cell_(computing)" title="Memory cell (computing)">memory cells</a>, which Kahng and Sze proposed could be used to produce <a href="EPROM" title="EPROM">reprogrammable ROM</a> (<a href="Read-only_memory" title="Read-only memory">read-only memory</a>).<sup id="cite_ref-computerhistory1971_6-0" class="reference"><a href="#cite_note-computerhistory1971-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> Initial applications of FGMOS was digital <a href="Semiconductor_memory" title="Semiconductor memory">semiconductor</a> <a href="Computer_memory" title="Computer memory">memory</a>, to store <a href="Nonvolatile_memory" class="mw-redirect" title="Nonvolatile memory">nonvolatile</a> data in <a href="EPROM" title="EPROM">EPROM</a>, <a href="EEPROM" title="EEPROM">EEPROM</a> and <a href="Flash_memory" title="Flash memory">flash memory</a>.

</p><p>In 1989, Intel employed the FGMOS as an analog nonvolatile memory element in its electrically trainable <a href="Artificial_neural_network" class="mw-redirect" title="Artificial neural network">artificial neural network</a> (ETANN) chip,<sup id="cite_ref-Holler_3-1" class="reference"><a href="#cite_note-Holler-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> demonstrating the potential of using FGMOS devices for applications other than digital memory.

</p><p>Three research accomplishments laid the groundwork for much of the current FGMOS circuit development:

</p>

<ul><li>Thomsen and Brooke's demonstration and use of <a href="Electron_tunneling" class="mw-redirect" title="Electron tunneling">electron tunneling</a> in a standard <a href="CMOS" title="CMOS">CMOS</a> double-<a href="Polysilicon" class="mw-redirect" title="Polysilicon">poly</a> process<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> allowed many researchers to investigate FGMOS circuits concepts without requiring access to specialized fabrication processes.</li>

<li>The <i>ν</i>MOS, or neuron-MOS, circuit approach by Shibata and Ohmi<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> provided the initial inspiration and framework to use capacitors for linear computations. These researchers concentrated on the FG circuit properties instead of the device properties, and used either <a href="Ultraviolet" title="Ultraviolet">UV</a> light to equalize charge, or simulated FG elements by opening and closing MOSFET switches.</li>

<li><a href="Carver_Mead" title="Carver Mead">Carver Mead</a>'s adaptive retina<sup id="cite_ref-Mead_2-2" class="reference"><a href="#cite_note-Mead-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> gave the first example of using continuously-operating FG programming/erasing techniques, in this case UV light, as the backbone of an adaptive circuit technology.</li></ul>

<div class="mw-heading mw-heading2"><h2 id="Structure">Structure</h2></div>

<p>An FGMOS can be fabricated by electrically isolating the gate of a standard MOS transistor, so that there are no resistive connections to its gate. A number of secondary gates or inputs are then deposited above the floating gate (FG) and are electrically isolated from it. These inputs are only capacitively connected to the FG, since the FG is completely surrounded by highly resistive material. So, in terms of its DC operating point, the FG is a floating node.

</p><p>For applications where the charge of the FG needs to be modified, a pair of small extra transistors are added to each FGMOS transistor to conduct the injection and tunneling operations. The gates of every transistor are connected together; the tunneling transistor has its source, drain and bulk terminals interconnected to create a capacitive tunneling structure. The injection transistor is connected normally and specific voltages are applied to create hot carriers that are then injected via an electric field into the floating gate.

</p><p>FGMOS transistor for purely capacitive use can be fabricated on N or P versions. <sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup>

For charge modification applications, the tunneling transistor (and therefore the operating FGMOS) needs to be embedded into a well, hence the technology dictates the type of FGMOS that can be fabricated.

</p>

<div class="mw-heading mw-heading2"><h2 id="Modeling">Modeling</h2></div>

<div class="mw-heading mw-heading3"><h3 id="Large_signal_DC">Large signal DC</h3></div>

<p>The equations modeling the DC operation of the FGMOS can be derived from the equations that describe the operation of the MOS transistor used to build the FGMOS. If it is possible to determine the voltage at the FG of an FGMOS device, it is then possible to express its drain to source current using standard MOS transistor models. Therefore, to derive a set of equations that model the large signal operation of an FGMOS device, it is necessary to find the relationship between its effective input voltages and the voltage at its FG.

</p>

<div class="mw-heading mw-heading3"><h3 id="Small_signal">Small signal</h3></div>

<p>An <i>N</i>-input FGMOS device has <i>N</i>−1 more terminals than a MOS transistor, and therefore, <i>N</i>+2 small signal parameters can be defined: <i>N</i> effective input <a href="Transconductance" title="Transconductance">transconductances</a>, an output transconductance and a bulk transconductance. Respectively:

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<annotation encoding="application/x-tex">{\displaystyle g_{mi}={\frac {C_{i}}{C_{T}}}g_{m}\quad {\mbox{for}}\quad i=[1,N]}</annotation>

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</math></span><img src="./e194d0688d39a0f12d724e488ee4ce3ab966bbde.svg" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -2.338ex; width:30.007ex; height:5.843ex;" alt="{\displaystyle g_{mi}={\frac {C_{i}}{C_{T}}}g_{m}\quad {\mbox{for}}\quad i=[1,N]}" loading="lazy"></span></dd>

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<annotation encoding="application/x-tex">{\displaystyle g_{dsF}=g_{ds}+{\frac {C_{GD}}{C_{T}}}g_{m}}</annotation>

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</math></span><img src="./4f86c3a3b8b753e8d1f9771001546542e894ac35.svg" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -2.338ex; width:21.281ex; height:5.843ex;" alt="{\displaystyle g_{dsF}=g_{ds}+{\frac {C_{GD}}{C_{T}}}g_{m}}" loading="lazy"></span></dd>

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<annotation encoding="application/x-tex">{\displaystyle g_{mbF}=g_{mb}+{\frac {C_{GB}}{C_{T}}}g_{m}}</annotation>

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</math></span><img src="./2038bf86b9ce392f960577ecaf51e713256e4a2f.svg" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -2.338ex; width:22.202ex; height:5.843ex;" alt="{\displaystyle g_{mbF}=g_{mb}+{\frac {C_{GB}}{C_{T}}}g_{m}}" loading="lazy"></span></dd></dl>

<p>where <span class="mwe-math-element mwe-math-element-inline"><span class="mwe-math-mathml-inline mwe-math-mathml-a11y" style="display: none;"><math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle C_{T}}">

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<annotation encoding="application/x-tex">{\displaystyle C_{T}}</annotation>

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</math></span><img src="./f6003ca59bfce8f624dd45e8ee023d098c7923cb.svg" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.671ex; width:3.051ex; height:2.509ex;" alt="{\displaystyle C_{T}}" loading="lazy"></span> is the total capacitance seen by the floating gate. These equations show two drawbacks of the FGMOS compared with the MOS transistor:

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<ul><li>Reduction of the input transconductance</li>

<li>Reduction of the output resistance</li></ul>

<div class="mw-heading mw-heading2"><h2 id="Simulation">Simulation</h2></div>

<p>Under normal conditions, a floating node in a circuit represents an error because its initial condition is unknown unless it is somehow fixed. This generates two problems:

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<ol><li>It is not easy to simulate these circuits</li>

<li>An unknown amount of charge might stay trapped at the floating gate during the fabrication process which will result in an unknown initial condition for the FG voltage.</li></ol>

<p>Among the many solutions proposed for the computer simulation, one of the most promising methods is an Initial Transient Analysis (ITA) proposed by Rodriguez-Villegas,<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> where the FGs are set to zero volts or a previously known voltage based on the measurement of the charge trapped in the FG after the fabrication process. A transient analysis is then run with the supply voltages set to their final values, letting the outputs evolve normally. The values of the FGs can then be extracted and used for posterior small-signal simulations, connecting a voltage supply with the initial FG value to the floating gate using a very-high-value inductor.

</p>

<div class="mw-heading mw-heading2"><h2 id="Applications">Applications</h2></div>

<p>The usage and applications of the FGMOS can be broadly classified in two cases. If the charge in the floating gate is not modified during the circuit usage, the operation is capacitively coupled.

</p><p>In the capacitively coupled regime of operation, the net charge in the floating gate is not modified. Examples of application for this regime are single transistor adders, DACs, multipliers and logic functions, and variable threshold inverters.

</p><p>Using the FGMOS as a programmable charge element, it is commonly used for <a href="Non-volatile_storage" class="mw-redirect" title="Non-volatile storage">non-volatile storage</a> such as <a href="Flash_memory" title="Flash memory">flash</a>, <a href="EPROM" title="EPROM">EPROM</a> and <a href="EEPROM" title="EEPROM">EEPROM</a> memory. In this context, floating-gate MOSFETs are useful because of their ability to store an electrical charge for extended periods of time without a connection to a power supply. Other applications of the FGMOS are neuronal computational element in <a href="Neural_network" title="Neural network">neural networks</a>, analog storage element and <a href="Digital_potentiometer" title="Digital potentiometer">e-pots</a>.

</p>

<ul><li><a href="Charge_trap_flash" title="Charge trap flash">Charge trap flash</a></li>

<li><a href="MOSFET" title="MOSFET">MOSFET</a></li>

<li><a href="SONOS" title="SONOS">SONOS</a></li></ul>

<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>

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</style><cite class="citation journal cs1"><a rel="nofollow" class="external text" href="https://onlinelibrary.wiley.com/doi/full/10.1002/aelm.201800726">"Tunneling: New Floating Gate Memory with Excellent Retention Characteristics"</a>. <i><a href="Wiley_Online_Library" class="mw-redirect" title="Wiley Online Library">Wiley Online Library</a></i>. <a href="Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://doi.org/10.1002%2Faelm.201800726">10.1002/aelm.201800726</a></span>. <a href="S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:139369906">139369906</a><span class="reference-accessdate">. Retrieved <span class="nowrap">19 June</span> 2019</span>.</cite></span>

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<li id="cite_note-Mead-2"><span class="mw-cite-backlink">^ <a href="#cite_ref-Mead_2-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-Mead_2-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-Mead_2-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><cite id="CITEREFMeadIsmail1989" class="citation book cs1">Mead, Carver A.; Ismail, Mohammed, eds. (May 8, 1989). <a rel="nofollow" class="external text" href="http://fennetic.net/irc/Christopher%20R.%20Carroll%20Carver%20Mead%20Mohammed%20Ismail%20Analog%20VLSI%20Implementation%20of%20Neural%20Systems.pdf"><i>Analog VLSI Implementation of Neural Systems</i></a> <span class="cs1-format">(PDF)</span>. The Kluwer International Series in Engineering and Computer Science. Vol. 80. Norwell, MA: <a href="Kluwer_Academic_Publishers" class="mw-redirect" title="Kluwer Academic Publishers">Kluwer Academic Publishers</a>. <a href="Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1007%2F978-1-4613-1639-8">10.1007/978-1-4613-1639-8</a>. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>978-1-4613-1639-8</bdi>.</cite></span>

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<li id="cite_note-Holler-3"><span class="mw-cite-backlink">^ <a href="#cite_ref-Holler_3-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-Holler_3-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text">M. Holler, S. Tam, H. Castro, and R. Benson, "An electrically trainable artificial neural network with 10240 'floating gate' synapses", <i>Proceedings of the International Joint Conference on Neural Networks</i>, Washington, D.C., vol. II, 1989, pp. 191–196</span>

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<li id="cite_note-computerhistory-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-computerhistory_4-0">^</a></b></span> <span class="reference-text"><cite class="citation journal cs1"><a rel="nofollow" class="external text" href="https://www.computerhistory.org/siliconengine/metal-oxide-semiconductor-mos-transistor-demonstrated/">"1960 - Metal Oxide Semiconductor (MOS) Transistor Demonstrated"</a>. <i>The Silicon Engine</i>. <a href="Computer_History_Museum" title="Computer History Museum">Computer History Museum</a>.</cite></span>

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<li id="cite_note-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-5">^</a></b></span> <span class="reference-text"><cite id="CITEREFKahngSze1967" class="citation journal cs1"><a href="Dawon_Kahng" title="Dawon Kahng">Kahng, Dawon</a>; <a href="Simon_Sze" title="Simon Sze">Sze, Simon Min</a> (1967). "A floating gate and its application to memory devices". <i><a href="The_Bell_System_Technical_Journal" class="mw-redirect" title="The Bell System Technical Journal">The Bell System Technical Journal</a></i>. <b>46</b> (6): <span class="nowrap">1288–</span>1295. <a href="Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1002%2Fj.1538-7305.1967.tb01738.x">10.1002/j.1538-7305.1967.tb01738.x</a>.</cite></span>

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<li id="cite_note-computerhistory1971-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-computerhistory1971_6-0">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.computerhistory.org/storageengine/reusable-semiconductor-rom-introduced/">"1971: Reusable semiconductor ROM introduced"</a>. <i><a href="Computer_History_Museum" title="Computer History Museum">Computer History Museum</a></i><span class="reference-accessdate">. Retrieved <span class="nowrap">19 June</span> 2019</span>.</cite></span>

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<li id="cite_note-7"><span class="mw-cite-backlink"><b><a href="#cite_ref-7">^</a></b></span> <span class="reference-text">A. Thomsen and M.A. Brooke, "A floating-gate MOSFET with tunneling injector fabricated using a standard double-polysilicon CMOS process," <a href="IEEE_Electron_Device_Letters" title="IEEE Electron Device Letters">IEEE Electron Device Letters</a>, vol. 12, 1991, pp. 111-113</span>

</li>

<li id="cite_note-8"><span class="mw-cite-backlink"><b><a href="#cite_ref-8">^</a></b></span> <span class="reference-text">T. Shibata and T. Ohmi, "A functional MOS transistor featuring gate-level weighted sum and threshold operations", <i>IEEE Transactions on Electron Devices</i>, vol. 39, no. 6, 1992, pp. 1444–1455</span>

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<cite id="CITEREFJanwadkar2017" class="citation web cs1">Janwadkar, Sudhanshu (2017-10-24). <a rel="nofollow" class="external text" href="https://www.slideshare.net/shudhanshu29/fabrication-of-floating-gate-mos-flotox">"Fabrication of Floating Gate MOS (FLOTOX)"</a>. <i>www.slideshare.net</i>.</cite></span>

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<li id="cite_note-10"><span class="mw-cite-backlink"><b><a href="#cite_ref-10">^</a></b></span> <span class="reference-text">Rodriguez-Villegas, Esther. Low Power and Low Voltage Circuit Design with the FGMOS Transistor</span>

</li>

</ol></div></div>

<div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2></div>

<ul><li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20110105165103/http://etd.gatech.edu/theses/available/etd-08062006-001021/unrestricted/ozalevli_erhan_200612_phd.pdf">EXPLOITING FLOATING-GATE TRANSISTOR PROPERTIES IN ANALOG AND MIXED-SIGNAL CIRCUIT DESIGN</a></li>

<li><a rel="nofollow" class="external text" href="http://computer.howstuffworks.com/rom4.htm">Howstuffworks "How ROM Works"</a></li>

<li><a rel="nofollow" class="external text" href="http://www.cs.washington.edu/homes/diorio/Publications/CoAuthConfPapers/PaulHasler/Floatgate_dev.pdf">Floating Gate Devices</a></li>

<li><a rel="nofollow" class="external text" href="https://www.amazon.com/dp/3639134109">FLOATING-GATE TRANSISTORS IN ANALOG AND MIXED-SIGNAL CIRCUIT DESIGN</a></li>

<li><a rel="nofollow" class="external text" href="https://www.amazon.com/dp/3836441772">Tunable and reconfigurable circuits using floating-gate transistors</a></li></ul></div><div><div class="zim-footer">

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